Increasing Carrier Lifetimes for High-voltage Silicon Carbide

Researchers in Japan have been developing ways to increase minority carrier lifetimes in lightly doped silicon carbide (SiC) with a view to insulated-gate bipolar transistors (IGBTs) [Tetsuya Miyazawa et al, J. Appl. Phys., vol118, p085702, 2015]. Such devices are being developed to handle very high voltages beyond 10kV for electric power transmission and distribution.

To handle high voltages, devices need a low resistance but relatively thick drift layer. The resistance of the drift layer is adversely affected by the short minority carrier lifetime typically achieved with SiC, particularly p-type. However, devices with n-type drift layers suffer from the high resistance of p-type substrates.

The team from Central Research Institute of Electric Power Industry (CRIEPI), Kansai Electric Power Co Inc, and National Institute of Advanced Industrial Science and Technology explored ways to create structures for both p- and n-type IGBTs to overcome these drawbacks.

A vertical hot-wall chemical vapor deposition (CVD) reactor was used for epitaxy on 3-inch 4H silicon-face n+-SiC with 4° offcut for both devices. Silane and propane were the silicon and carbon sources, respectively. The carrier gas consisted of hydrogen and hydrogen chloride. The p- and n-type dopants were trimethyl-aluminium and nitrogen, respectively.

Particular care was needed to control the TMA delivery for low-concentration p-type doping (~1014/cm3) and the researchers developed a modified feed system that involved diluting the hydrogen containing the TMA with more hydrogen before delivering it to the CVD reactor.

A structure suitable for a p-IGBT (Figure 1) was grown first up to a 180μm p- drift layer that was subsequently trimmed back to 155μm by chemical mechanical polishing (CMP). Carrier lifetime enhancement was achieved for some devices (sample B) by carbon implantation to a depth of 250nm and annealing in argon. The surface was protected with a carbon cap that was later removed by ashing. The implanted region was also removed by reactive ion etch (RIE) of a 1μm layer.

PiN diodes were fabricated as test vehicles for the structure and related processing by growing and p+ anode and p++ contact layers. The devices were fabricated with 4mmx4mm mesas. After contact metal deposition the devices were then singulated into chips. Sample B devices were also subjected to hydrogen annealing at 800°C for 10 minutes between contact metal deposition and singulation.

The TRPL results for the n-PiN growth sequence (Table 1) showed the final structure as having a minority carrier lifetime of 10.7μs. The n-PiN had a much lower voltage drop at room temperature of 5.5V for 100A/cm2 current. Increasing the temperature reduced the voltage drop to less than 3.0V at 250°C. The differential on-resistance was 17mΩ-cm2 at room temperature and 1.9mΩ-cm2 at 250°C.

Decreasing the device area to 1.0mmx1.0mm increased the voltage drop to the range 6.5V-8.0V. The researchers attribute this to carrier recombination at the mesa periphery. Surface passivation to reduce this effect should improve performance.